High Performance Memory System for High Ilp Microarchitectures

A new memory system is proposed that greatly widens the von Neumann bottleneck for uniprocessors with high bandwidth requirements, especially those processors exhibiting large degrees of Instruction Level Parallelism (ILP). The new system has high bandwidth and low latency, and is not costly. Further, minimal ordering of memory accesses is achieved, in that only accesses to the same main memory location are sequentialized; accesses to diierent addresses are independent. Memory-mapped I/O accesses are also taken into consideration. The system is described in an overview, discussing its general architecture, and then the details of the communications protocol are given. Lastly, performance of the system is discussed.